1. Field of the Invention
The present invention relates generally to a multiplex circuit having a single selection signal and to a method of generating a MUX output signal with a single selection signal.
2. Description of the Related Art
In digital technology, various logic techniques are being employed for high-speed operations. An example of these various logic devices is a transmission gate which is used to transmit a signal. A dual-rail method may be adopted for high-speed signal transmission operation for the transmission gate. In general, the dual-rail method transmits an output signal from a received input signal in response to a transmission gate enabling signal and a complementary enabling signal. The enabling signal (which may also be referred to as a ‘selection signal’) enables the transmission gate; the complementary enabling signal is an inverted version of the enabling signal. The area of the transmission gate may become substantially large due to the generation of the complementary enabling signal. The gate area increases due to the routing of this complementary enabling signal through the transmission gate, which may be disadvantageous for high speed logic operations.
Another method for high-speed signal transmission operation for the transmission gate is known as a single-rail method. The single-rail method employs an inverter to produce the complementary enabling signal within the ‘single-rail’. The inverter outputs the complimentary enabling signal after the transmission gate enabling signal is input to the inverter. However, use of the inverter in this single-rail method may also adversely affect high-speed operations in the transmission gate and/or the power used for high-speed logic operations. This type of transmission gate may typically be used in what is known as a multiplex (MUX) circuit.
FIG. 1 is a diagram of a conventional art MUX circuit. Referring to FIG. 1, in response to a selection signal S, a MUX circuit 100 may selectively transmit a first input signal A or a second input signal B as an output signal SO. The MUX circuit 100 may includes a first inverter 101 that produces a complementary selection signal SB by inverting the selection signal S; a second inverter 102 and a third inverter 103. The second inverter 102 may be configured to receive the first input signal A, and the third inverter 103 may be configured to receive the second input signal B.
MUX circuit 100 may include first and second transmission gates 104 and 105. In response to the selection signal S and the complementary selection signal SB, first and second transmission gates 104 and 105 may transmit outputs of the corresponding second inverter 102 and third inverter 103. A fourth inverter 106 may be configured to invert the outputs of the first and second transmission gates 104 and 105, respectively. These outputs are combined and input to fourth inverter 106 so as to generate the output signal SO, as shown in FIG. 1.
The conventional art MUX circuit 100 requires that the selection signal S and complementary selection signal SB (which enable the transmission gates 104 and 105) be transmitted to the transmission gates 104 and 105 later than input signals AB and BB are transmitted to the transmission gate for safe transmission of the signals. That is, transmission of the selection signal S and the complementary selection signal SB to the transmission gates 104 and 105 is delayed.
The time at which the complementary selection signal SB is generated is a function of the operational characteristics of the first inverter 101. Since the complementary selection signal SB is generated after a delay time of the first inverter 101, the complementary selection signal SB may interfere with the high-speed signal transmission operation of the MUX circuit 100.